View AD8314ARMZ-REEL7_3417169.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8314 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 100 mhz?.7 ghz 45 db rf detector/controller features complete rf detector/controller function typical range C58 dbv to C13 dbv C45 dbm to 0 dbm re 50 frequency response from 100 mhz to 2.7 ghz temperature-stable linear-in-db response accurate to 2.7 ghz rapid response: 70 ns to a 10 db step low power: 12 mw at 2.7 v power-down to 20 a applications cellular handsets (tdma, cdma, gsm) rssi and tssi for wireless terminal devices transmitter power measurement and control product description the ad8314 is a complete low cost subsystem for the measure- ment and control of rf signals in the frequency range of 100 mhz to 2.7 ghz, with a typical dynamic range of 45 db, intended for use in a wide variety of cellular handsets and other wireless devices. it provides a wider dynamic range and better accuracy than possible using discrete diode detectors. in particular, its temperature stabil- ity is excellent over the full operating range of ?0 c to +85 c. its high sensitivity allows control at low power levels, thus reducing the amount of power that needs to be coupled to the detector. it is essentially a voltage-responding device, with a typical signal range of 1.25 mv to 224 mv rms or ?8 dbv to ?3 dbv. this is equivalent to ?5 dbm to 0 dbm re 50 ? . for convenience, the signal is internally ac-coupled, using a 5 pf capacitor to a load of 3 k ? in shunt with 2 pf. this high-pass coupling, with a corner at approximately 16 mhz, determines the lowest operating frequency. thus, the source may be dc- grounded. the ad8314 provides two voltage outputs. the first, called v_up, increases from close to ground to about 1.2 v as the input signal level increases from 1.25 mv to 224 mv. this output is intended for use in measurement mode. consult the appli- cations section of this data sheet for information on use in this mode. a capacitor may be connected between the v_up and fltr pins when it is desirable to increase the time interval over which averaging of the input waveform occurs. the second output, v_dn, is an inversion of v_up, but with twice the slope and offset by a fixed amount. this output starts at about 2.25 v (pro vided the supply voltage is 3.3 v) for the minimum input and falls to a value close to ground at the maximum input. this output is intended for analog control loop applications. a setpoint voltage is applied to vset and v_dn is then used to control a vga or power amplifier. here again, an external filter capacitor may be added to extend the averaging time. consult the applic ations section of this data sheet for information on use in this mode. the ad8314 is available in micro_soic and chip scale packages and consumes 4.5 ma from a 2.7 v to 5.5 v supply. when pow- ered down, the typical sleep current is 20 a. functional block diagram 10db offset compensation v-i i-v rfin comm (paddle) vpos x2 enbl v dn v up vset fltr ad8314 10db 10db 10db band-gap reference det det det det det
C2C rev. a ad8314?pecifications (v s = 3 v, t a = 25 c, unless otherwise noted) parameter conditions min typ max unit overall function frequency range 1 to meet all speci?ations 0.1 2.5 ghz input voltage range internally ac-coupled 1.25 224 mv rms equivalent power range 52.3 ? external termination ?5 0 dbm logarithmic slope main output, v_up, 100 mhz 2 18.85 21.3 23.35 mv/db logarithmic intercept main output, v_up, 100 mhz ?8 ?2 ?6 dbv equivalent dbm level 52.3 ? external termination ?5 ?9 ?3 dbm input interface (pin rfin) dc resistance to comm 100 k ? inband input resistance f = 0.1 ghz 3 k ? input capacitance f = 0.1 ghz 2 pf main output (pin v_up) voltage range v_up connected to vset 0.01 1.2 v minimum output voltage no signal at rfin, r l 10 k ? 0.01 0.02 0.05 v maximum output voltage 3 r l 10 k ? 1.9 2 v general limit 2.7 v v s 5.5 v v s 1.1 v s ? v available output current sourcing/sinking 1/0.5 2/1 ma response time 10%?0%, 10 db step 70 ns residual rf (at 2f) f = 0.1 ghz (worst condition) 100 v inverted output (pin v_dn) gain referred to v_up v dn = 2.25 v ?2 v up ? minimum output voltage v s 3.3 v 0.01 0.05 0.1 v maximum output voltage v s 3.3 v 4 2.1 2.2 2.5 v available output current sourcing/sinking 4/100 6/200 ma/ a output-referred noise rf input = 2 ghz, ?3 dbv, f noise = 10 khz 1.05 v/ hz response time 10%?0%, 10 db input step 70 ns full-scale settling time ?0 dbm to 0 dbm input step, to 95% 150 ns setpoint input (pin vset) voltage range corresponding to central 40 db 0.15 1.2 v input resistance 710 k ? logarithmic scale factor f = 0.900 ghz 20.7 mv/db f = 1.900 ghz 19.7 mv/db enable interface (pin enbl) logic level to enable power hi condition, ?0 c t a +85 c 1.6 v pos v input current when hi 2.7 v at enbl, ?0 c t a +85 c 20 300 a logic level to disable power lo condition, ?0 c t a +85 c ?.5 0.8 v power interface (pin vpos) supply voltage 2.7 3.0 5.5 v quiescent current 3.0 4.5 5.7 ma over temperature ?0 c t a +85 c 2.7 4.4 6.6 ma total supply current when disabled 20 95 a over temperature ?0 c t a +85 c40 a notes 1 for a discussion on operation at higher frequencies, see applications section. 2 mean and standard deviation speci?ations are available in table i. 3 increased output possible when using an attenuator between v_up and vset to raise the slope. 4 refer to tpc 19 for details. speci?ations subject to change without notice.
ad8314 C3C rev. a ordering guide temperature package package branding model range description option information ad8314arm ?0 c to +85 c tube, 8-lead micro_soic rm-8 j5a ad8314arm-reel 13" tape and reel ad8314arm-reel7 7" tape and reel ad8314-eval evaluation board ad8314acp-reel ?0 c to +85 c 13" tape and reel cp-8 j5a 8-lead chip scale package ad8314acp-reel7 7" tape and reel ad8314acp-eval evaluation board absolute maximum ratings * supply voltage vpos . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v_up, v_dn, vset, enbl . . . . . . . . . . . . . . . . 0 v, vpos input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 v rms equivalent power . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 dbm internal power dissipation . . . . . . . . . . . . . . . . . . . . 200 mw ja ( so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 c/w ja (csp, paddle soldered) . . . . . . . . . . . . . . . . . . . . 80 c/w ja (csp, paddle not soldered) . . . . . . . . . . . . . . . . 200 c/w maximum junction temperature . . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) so . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c csp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8314 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions pin name function 1 rfin rf input 2 enbl connect pin to v s for normal operation. connect pin to ground for disable mode. 3 vset s etpoint input for operation in controller mode. to operate in detector mode connect vset to v_up. 4 fltr connection for an external capacitor to slow the response of the output. capacitor is con- nected between fltr and v_up. 5 comm device common (ground) 6 v_up logarithmic output. output voltage increases with increasing input amplitude. 7 v_dn inversion of v_up, governed by the following equation: v_dn = 2.25 v 2 v up . 8 vpos positive supply voltage (v s ), 2.7 v to 5.5 v. pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 rfin enbl vset vpos v dn v up comm fltr ad8314
ad8314 C4C rev. a input amplitude ?dbv 1.2 0 ?5 ? ?5 v up ?volts ?5 ?5 ?5 ?5 ?5 1.0 0.8 0.6 0.4 0.2 (?2dbm) (?dbm) 2.5ghz 1.9ghz 0.9ghz 0.1ghz tpc 1. v up vs. input amplitude input amplitude dbv 1.2 0 70 0 60 ( 47dbm) v up volts 50 40 30 20 10 (+3dbm) 1.0 0.8 0.6 0.4 0.2 30 c +85 c +25 c +25 c 30 c 3 3 2 1 0 1 2 slope and intercept normalized at +25 c and applied to 30 c and +85 c error db tpc 2. v up and log conformance vs. input amplitude at 0.1 ghz; C30 c, +25 c, and +85 c input amplitude dbv 1.2 0 70 0 60 ( 47dbm) v up volts 50 40 30 20 10 (+3dbm) 1.0 0.8 0.6 0.4 0.2 30 c +85 c +25 c 3 3 2 1 0 1 2 slope and intercept normalized at +25 c and applied to 30 c and +85 c error db tpc 3. v up and log conformance vs. input amplitude at 0.9 ghz; C30 c, +25 c, and +85 c typical performance characteristics input amplitude dbv 4 4 70 0 60 error db 50 40 30 20 10 1 0 1 2 3 2.5ghz 1.9ghz 0.9ghz ( 47dbm) (+3dbm) 0.1ghz 2 3 tpc 4. log conformance vs. input amplitude input amplitude dbv 1.2 0 70 0 60 ( 47dbm) v up volts 50 40 30 20 10 (+3dbm) 1.0 0.8 0.6 0.4 0.2 30 c +85 c +25 c 3 3 2 1 0 1 2 slope and intercept normalized at +25 c and applied to 30 c and +85 c error db tpc 5. v up and log conformance vs. input amplitude at 1.9 ghz; C30 c, +25 c, and +85 c input amplitude dbv 1.2 0 70 0 60 ( 47dbm) v up volts 50 40 30 20 10 (+3dbm) 1.0 0.8 0.6 0.4 0.2 30 c +85 c +25 c 3 3 2 1 0 1 2 slope and intercept normalized at +25 c and applied to 30 c and +85 c error db +85 c tpc 6. v up and log conformance vs. input amplitude at 2.5 ghz; C30 c, +25 c, and +85 c
ad8314 C5C rev. a frequency ghz 0 0.5 slope mv/db 1.0 22 21 20 19 18 30 c +85 c +25 c 1.5 2.0 2.5 23 tpc 7. slope vs. frequency; C30 c, +25 c, and +85 c v s volts 22 19 2.5 v up slope mv/db 21 20 2.5ghz 1.9ghz 0.9ghz 0.1ghz 3.0 3.5 4.0 4.5 5.0 5.5 tpc 8. v up slope vs. supply voltage frequency ghz 0 0.5 1.0 0 1.5 2.0 2.5 500 1000 1500 2000 2500 3000 3500 resistance 200 0 400 600 800 1000 1200 1400 x r || - jx || - j748 || - j106 || - j80 || - j141 r 3030 760 301 90 frequency (ghz) 0.1 0.9 1.9 2.5 r x reactance tpc 9. input impedance frequency ghz 0 0.5 1.0 75 30 c +85 c +25 c 1.5 2.0 2.5 70 65 60 55 v up intercept dbv tpc 10. v up intercept vs. frequency: C30 c, +25 c, and +85 c v s volts 67 2.5 v up intercept dbv 2.5ghz 1.9ghz 0.9ghz 0.1ghz 3.0 3.5 4.0 4.5 5.0 5.5 66 65 64 63 62 61 tpc 11. v up intercept vs. supply voltage v enbl volts 1 0.2 supply current ma increasing v enbl 0 1 2 3 4 5 6 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 decreasing v enbl &'()" 6(
:+ 6 ;#
ad8314 C6C rev. a 1 s per horizontal division v enbl 5v per vertical division v dn gnd v up gnd v enbl gnd v dn 500mv/vertical division v up 500mv/ vertical division average: 128 samples tpc 13. enbl response time 1 2 3 4 enbl rfin ad8314 rf out tek tds784c scope trig out hp8116a pulse generator 10mhz ref output ext trig nc = no connect 0.1 f nc 8 7 6 5 vset fltr v dn vpos comm v up tek p6204 fet probe tek p6204 fet probe 3.0v pulse out trig 52.3 33dbv hp8648b signal generator tpc 14. test setup for enbl response time frequency hz 80 10 amplitude db 0 phase de g rees 75 10 70 20 65 30 60 40 55 50 50 60 45 70 40 80 35 90 30 100 25 110 20 120 15 130 10 140 5 150 0 160 5 170 100 1k 10k 100k 1m 10m tpc 15. ac response from vset to v_dn 200mv per vertical division 100ns per horizontal division rf input average: 128 samples pulsed rf 0.1ghz, 13dbv gnd gnd v up 500mv/ vertical division v dn 1v/vertical division tpc 16. v up and v dn response time, C40 dbm to 0 dbm 1 2 3 4 enbl rfin ad8314 rf out tek tds784c scope trig out picosecond pulse labs pulse generator hp8648b signal generator pulse modulation mode 10mhz ref output ext trig nc = no connect 0.1 f nc 8 7 6 5 vset fltr v dn vpos comm v up tek p6204 fet probe tek p6204 fet probe 3.0v trig 52.3 out pulse mode in 3db 3.0v rf splitter tek p6204 fet probe 3db tpc 17. test setup for pulse response noise spectral density v/ hz frequency hz 10.0 0.1 100 1.0 1k 10k 100k 1m 10m 60dbm 40dbm 30dbm 20dbm rf input 70dbm 50dbm tpc 18. v dn noise spectral density
ad8314 C7C rev. a v s volts 2.3 1.7 2.7 v dn v 2.2 2.1 2.0 1.9 1.8 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 0ma 2ma 4ma 6ma tpc 19. maximum v dn voltage vs. v s by load current 1 s per horizontal division vpos and enable 2v per vertical division v up 500mv/vertical division v up v up 500mv/vertical division average: 128 samples v dn gnd v up gnd gnd tpc 20. power-on and power-off response, measurement mode hp8648b signal generator 1 2 3 4 enbl rfin ad8314 rf out tek tds784c scope trig out hp8116a pulse generator 10mhz ref output ext trig nc = no connect nc 8 7 6 5 vset fltr v dn vpos comm v up tek p6204 fet probe tek p6204 fet probe trig 52.3 pulse out 49.9 ad811 732 33dbv tpc 21. test setup for power-on and power-off response v s volts 2.3 1.7 2.7 v dn v 2.2 2.1 2.0 1.9 1.8 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 shading indicates 3 sigma &'("" => 6 # + 100ns per horizontal division 200mv per vertical division v dn average: 128 samples 2v per vertical division vpos and enable v dn gnd gnd &'("# '
?@ (

= 6&+ 1 2 3 4 enbl rfin ad8314 rf out tek tds784c scope trig out hp8112a pulse generator 10mhz ref output ext trig nc = no connect nc 8 7 6 5 vset fltr v dn vpos comm v up tek p6204 fet probe trig 52.3 +0.2 nc pulse out 49.9 732 hp8648b signal generator ad811 tpc 24. test setup for power-on response at v_dn output, controller mode with vset pin held low
ad8314 C8C rev. a table i. typical speci?ations at selected frequencies at 25 c (mean and sigma) 1 db dynamic range * (dbv) slope (mv/db) intercept (dbv) high point low point frequency (ghz) 0.1 21.3 0.4 62.2 0.4 11.8 0.3 59 0.5 0.9 20.7 0.4 63.6 0.4 13.8 0.3 61.4 0.4 1.9 19.7 0.4 66.3 0.4 19 0.7 64 0.6 2.5 19.2 0.4 62.1 0.7 16.4 1.7 61 1.3 * refer to figure 5. general description the ad8314 is a logarithmic ampli er (log amp) similar in design to the ad8313; further details about the structure and function may be found in the ad8313 data sheet and other log amps produced by analog devices. figure 1 shows the main fea- tures of the ad8314 in block schematic form. the ad8314 combines two key functions needed for the mea- surement of signal level over a moderately wide dynamic range. first, it provides the ampli cation needed to respond to small signals, in a chain of four ampli er/limiter cells, each having a small-signal gain of 10 db and a bandwidth of approximately 3.5 ghz. at the output of each of these ampli er stages is a full-wave recti er, essentially a square-law detector cell, that converts the rf signal voltages to a fluctuating current having an average value that increases with signal level. a further passive detector stage is added ahead of the rst stage. thus, there are ve detect ors, each separated by 10 db, spanning some 50 db of dynamic range. the overall accuracy at the extremes of this total range, viewed as the deviation from an ideal logarithmic response, that is, the law-conformance error , can be judged by reference to tpc 4, which shows that errors across the central 40 db are moderate. other curves show how the conformance to an ideal logarithmic function varies with supply voltage, temperature and frequency. the output of these detector cells is in the form of a differential current, making their summation a simple matter. it can easily be shown that such summation closely approximates a logarith- mic function. this result is then converted to a voltage, at pin v_up, through a high-gain stage. in measurement modes, this output is connected back to a voltage-to-current (v i) stage, in such a manner that v_up is a logarithmic measure of the rf input voltage, with a slope and intercept controlled by the design. for a xed termination resistance at the input of the ad8314, a given voltage corresponds to a certain power level. 10db offset compensation v-i i-v rfin comm (paddle) vpos x2 enbl v dn v up vset fltr ad8314 10db 10db 10db band-gap reference det det det det det figure 1. block schematic however, in using this part, it must be understood that log amps do not fundamentally respond to power. it is for this reason the dbv is used (decibels above 1 v rms) rather than the commonly used metric of dbm. while the dbv scaling is xed, independent of termination impedance, the corresponding power level is not. for example, 224 mv rms is always 13 dbv (with one further condition of an assumed sinusoidal waveform; see the applications section for more information about the effect of w aveform on logarithmic intercept), and it corresponds to a power of 0 dbm when the net impedance at the input is 50 ? . when this imped- ance is altered to 200 ? , the same voltage clearly represents a power level that is four times smaller (p = v 2 /r), that is, 6 dbm. note that dbv may be converted to dbm for the special case of a 50 ? system by simply adding 13 db (0 dbv is equivalent to +13 dbm). thus, the external termination added ahead of the ad8314 deter- mines the effective power scaling. this will often take the form of a simple resistor (52.3 ? will provide a net 50 ? input) but more elaborate matching networks may be used. this impedance de ter- mines the logarithmic intercept, the input power for which the output would cross the baseline (v_up = zero) if the function were continuous for all values of input. since this is n ever the case for a practical log amp, the intercept refers to the value ob tained by the minimum-error straight-line t to the actual graph of v_up versus p in (more generally, v in ). again, keep in mind that the quoted values assume a sinusoidal (cw) s ignal. where there is complex modulation, as in cdma, the calibration of the power response needs to be adjusted accordingly. where a true power (waveform-independent) response is needed, the use of an rms-responding detector, such as the ad 8361, should be considered. however, the logarithmic slope, the amount by which the output v_up changes for each decibel of input change (voltage or power) is, in principle, independent of waveform or termination impedance. in practice, it usually falls off somewhat at higher
ad8314 C9C rev. a frequencies, due to the declining gain of the ampli er stages and o ther effects in the detector cells. for the ad8314, the slope at low frequencies is nominally 21.3 mv/db, fa lling almost linearly w ith frequency to about 19.2 mv/db at 2.5 ghz. these values are sensibly independent of temperature (see tpc 7) and almost totally unaffected by the supply voltage from 2.7 v to 5.5 v (tpc 8). inverted output the second provision is the inclusion of an inverting ampli er to the output, for use in controller app lications. most power ampli ers require a gain-control bias that must decrease from a large positive value toward ground l evel as the power output is required to decrease. this control voltage, which appears at the pin v_dn, is not only of the opposite polarity to v_up, but also needs to have an offset added in order to determine its most posi- tive value when the power level (assumed to be monitored through a directional coupler at the output of the pa) is minimal. the starting value of v_dn is nominally 2.25 v, and it falls on a slope of twice that of v_up, in other words, 43 mv/db. figure 2 shows how this is achieved: the reference voltage that determines the maximum output is derived from the on-chip voltage reference, and is sub stantially independent of the sup- ply voltage or temperature. however, the full output cannot be attained for supply voltages under 3.3 v; tpc 19 shows this dependency. the relationship between v_up and v_dn is shown in figure 3. v i band-gap reference +2 vset fltr i v 1.125v v dn = 2.25v 2.0 v_up currents from detectors ad8314 v_up v_dn figure 2. output interfaces input amplitude dbv 0 60 volts 2.5 2.0 1.5 1.0 0.5 output for pa control 50 40 30 20 10 0 output for measurement v_up v_dn figure 3. showing v_up and v_dn relationship applications basic connections figure 4 shows connections for the basic measurement mode. a supply voltage of 2.7 v to 5.5 v is required. the supply to the vpos pin should be decoupled with a low inductance 0.1 f surface mount ceramic capacitor. a series resistor of about 10 ? may be added; this resistor will slightly reduce the supply voltage to the ad8314 (maximum current into the vpos pin is approxi- mately 9 ma when v_dn is delivering 5 ma). its use should be avoided in applications where the power supply voltage is very low (i.e., 2.7 v). a series inductor will provide similar power supply ltering with minimal drop in supply voltage. 1 2 3 4 enbl rfin ad8314 8 7 6 5 vset fltr v dn vpos comm v up 0.1 f optional (see text) optional (see text) v s v dn v up c f v s 52.3 input figure 4. basic connections for operation in measurement mode the enbl pin is here connected to vpos. the ad8314 may be disabled by pulling this pin to ground when the chip current is reduced to about 20 a from its normal value of 4.5 ma. the logic threshold is around +v s /2 and the enable function occurs in about 1.5 s. note, however, further settling time is generally needed at low input levels. the ad8314 has an internal input coupling capacitor. this eliminates the need for external ac-coupling. a broadband input match is achieved in this example by connecting a 52.3 ? resis- tor between rfin and ground. this resistance combines with the internal input impedance of approximately 3 k ? to give an overall broadband input resistance of 50 ? . several other coupling methods are possible; these are described in the input coupling section. the measurement mode is selected by connecting vset to v_up, which establishes a feedback path and sets the logarithmic slope to its nominal value. the peak voltage range of the measurement extends from 58 dbv to 13 dbv at 0.9 ghz, and only slightly less at higher frequencies up to 2.5 ghz. thus, using the 50 ? termination, the equivalent power range is 45 dbm to 0 dbm. at a slope of 21.5 mv/db, this would amount to an output span of 967 mv. figure 5 shows the transfer function for v_up at a supply voltage of 3 v, and input frequency of 0.9 ghz. v_dn, which will generally not be used when the ad8314 is used in the measurem ent mode, is essentially an inverted version of v_up. the voltage on v_up and v_dn are related by the equation: vvv dn up = 225 2 . while v_dn can deliver up to 6 ma, the load resistance on v_up should not be lower than 10 k ? in order that the full-scale output of 1 v can be genera ted with the limited available current of 200 a max. figure 5 shows the logarithmic conformance under the same conditions.
ad8314 C10C rev. a input amplitude dbv 1.2 0 70 0 60 ( 47dbm) v up volts 50 40 30 20 10 (+3dbm) 1.0 0.8 0.6 0.4 0.2 v s = 3v r t = 52.3 3 3 2 1 0 1 2 1db dynamic range error db 3db dynamic range intercept figure 5. v up and log conformance error vs. input level vs. input level at 900 mhz transfer function in terms of slope and intercept the transfer function of the ad8314 is characterized in terms of its slope and intercept. the logarithmic slope is de ned as the change in the rssi output voltage for a 1 db change at the input. for the ad8314, slope is nominally 21.5 mv/db. so a 10 db change at the input results in a change at the output of approxi- mately 215 mv. the plot of log conformance (figure 5) shows the range over which the device maintains its constant slope. the dynamic range can be de ned as the range over which the error remains within a ce rtain band, usually 1 db or 3 db. in figure 5, for example, the 1 db dynamic range is approxim ately 50 db (from 13 dbv to 63 dbv). the intercept is the point at which the extrapolated linear response would intersect the horizontal axis (figure 5). using the slope and intercept, the output voltage can be calculated for any input level within the speci ed input range using the equation: vv pp up slope in o = () where v up is the demodulated and ltered rssi output, v slope is the logarithmic slope, expressed in v/db, p in is the input sig- nal, expressed in decibels relative to some reference level (either dbm or dbv in this case) and p o is the logarithmic intercept, expressed in decibels relative to the same reference level. for example, at an input level of 40 dbv ( 27 dbm), the output voltage will be: v out = 0.020 v/db [ 40 dbv ( 63 dbv )] = 0.46 v dbv vs. dbm the most widely used convention in rf systems is to specify power in dbm, that is, decibels above 1 mw in 50 ? . speci cation of log amp input levels in terms of power is strictly a concession to popular convention; they do not respond to power (tacitly power absorbed at the input ), but to the input voltage. the use of dbv, de ned as decibels with respect to a 1 v rms sine wave , is more pre- cise, although this is still not unambiguous because waveform is also involved in the response of a log amp, which, for a complex input (such as a cdma signal), will not follow the rms value exactly. since most users specify rf signals in terms of power more speci cally, in dbm/50 ? both dbv and dbm are used in specifying the performance of the ad8314, showing equiva lent dbm levels for the special case of a 50 ? environment. values in dbv are converted to dbm re 50 ? by adding 13. filter capacitor the video bandwidth of both v_up and v_dn is approximately 3.5 mhz. in cw applications where the input frequency is much higher than this, no further ltering of the demodulated signal will be required. where there is a low frequency modulation of the carrier amplitude, however, the low-pass corner must be reduced by the addition of an external lter capacitor, c f (see figure 4). the video bandwidth is related to c f by the equation video bandwidth kpfc f = + 1 213 35 ? (. ) operating in controller mode figure 6 shows the basic connections for operation in the con trol- ler mode and figure 7 shows a block diagram of a typical controller mode application. the feedback from v_up to vset is broken and the desired setpoint voltage is applied to vset from the con trol- ling source (often this will be a dac). v dn will rail high (2.2 v on a 3.3 v supply, 1.9 v on a 2.7 v supply) when the applied power is less than the value corresponding to the setpoint voltage. when the input power slightly exceeds this value, v dn would, in the absence of the loop via the power ampli er gain pin, decrease rapidly toward ground. in the closed loop, however, the re duc- tion in v dn causes the power ampli er to reduce its output. this restores a balance between the actual power level sensed at the input of the ad8314 and the demanded value determined by the setpoint. this assumes that the gain control sense of the variable gain ele- ment is positive, that is, an increasing voltage from v_dn will tend to increase gain. the output swing and current sourcing capability of v_dn are shown in tpcs 19 and 22. 1 2 3 4 enbl rfin ad8314 8 7 6 5 vset fltr v dn vpos comm v up v s vdn v s input vset c f 0.1 f 52.3 figure 6. basic connections for operation in controller mode dac fltr v up vset ad8314 directional coupler power amplifier rf input gain control voltage rfin v dn c f 52.3 figure 7. typical controller mode application
ad8314 C11C rev. a the relationship between the input level and the setpoint voltage follows from the nominal transfer function of the device (v up vs. input amplitude, see tpc 1). for example, a voltage of 1 v on vset is demanding a power level of 0 dbm at rfin. the corre- sponding power level at the output of the power amplifier will be greater than this amount due to the attenuation through the direc- tional coupler. when connected in a pa control loop, as shown in figure 7, the voltage v up is not explicitly used, but is implicated in again setting up the required averaging time, by choice of c f . however, now the effective loop response time is a much more complicated function of the pa s gain-control characteristics, which are very nonlin ear. a complete solution requires speci c knowledge of the power ampli er. the transient response of this control loop is determined by the lter capacitor, c f . when this is large, the loop will be u ncon- ditionally stable (by virtue of the dominant pole gene rated by this capacitor), but the response will be sluggish. the minimum value ensuring stability should be used, requiring full attention to the particulars of the power ampli er control function. because this is invariably nonlinear, the choice must be made for the worst-case condition, which usually corresponds to the smallest output from the pa, w here the gain function is st eepest. in practice, an improvement in loop dynamics can often be achieved by adding a response zero, formed by a resistor in series with c f . power-on and enable glitch as already mentioned, the ad8314 can be put into a low power mode by pulling the enbl pin to ground. this reduces the quiescent current from 4.5 ma to 20 a. alternatively, the supply can be turned off completely to eliminate the quiescent current. tpcs 13 and 23 show the behavior of the v_dn output under these two conditions (in tpc 23, enbl is tied to vpos). the glitch that results in both cases can be reduced by loading the v_dn output. input coupling options the internal 5 pf coupling capacitor of the ad8314, along with the low frequency input impedance of 3 k ? , gives a high-pass input corner frequency of approximately 16 mhz. this sets the mini- mum operating frequency. figure 8 shows three options for input coupling. a broadband resistive match can be implemented by connecting a shunt resistor to ground at rfin ( figure 8a). this 52.3 ? resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the ad8314 (3 k ? 2 pf) to give a broadband input im pedance of 50 ? . while the input resistance and capaci- tance (c in and r in ) will vary by approximately 20% f rom device to device, the dom inance of the external shunt resistor means that the variation in the overall input impedance will be close to the tolerance of the external resistor. at frequencies above 2 ghz, the input impedance drops below 250 ? (see tpc 9), so it is appropriate to use a larger value of shunt resistor. this value is calculated by plotting the input impedance (resistance and capacitance) on a smith chart and choosing the best value of shunt resistor to bring the input imped- ance closest to the center of the chart. at 2.5 ghz, a shunt resistor of 165 ? is recommended. a reactive match can also be implemented as shown in figure 8b. this is not recommended at low frequencies as device toler- ances will dramatically vary the quality of the match because of the large input resistance. for low frequencies, option a or option c (see below) is recommended. in figure 8b, the matching components are drawn as general reactances. depending on the frequency, the input impedance at that frequency and the availability of standard value components, either a capacitor or an inductor will be used. as in the previous case, the input impedance at a particular frequency is plotted on a smith chart and matching components are chosen (shunt or series l, shunt or series c) to move the impedance to the center of the chart. table ii gives standard component values for some popular frequencies. matching components for other frequencies can be calculated using the input resistance and reac- tance data over frequency which is given in tpc 9. note that the reactance is plotted as though it appears in paral lel with the input impedance (which it does because the reactance is primarily due to input capacitance). the impedance matching characteristics of a reactive matching network provide voltage gain ahead of the ad8314; this increases the device sensitivity (see table ii). the voltage gain is calculated using the equation: voltage gain r r db = 20 2 1 10 log where r 2 is the input impedance of the ad8314 and r 1 is the source impedance to which the ad8314 is being matched. note that this gain will only be achieved for a perfect match. component toleran ces and the use of standard values will tend to reduce the gain. r shunt 52.3 c in ad8314 50 50 source r in c c rfin v bias a. broadband resistive 50 source c in ad8314 50 r in c c rfin v bias x2 x1 b. narrowband reactive c in ad8314 r in c c rfin v bias r attn stripline c. series attenuation figure 8. input coupling options figure 8c shows a third method for coupling the input signal into the ad8314, applicable in applications where the input signal is larger than the input range of the log amp. a series resistor, connected to the rf source, combines with the input impedance of the ad8314 to resistively divide the input signal being a pplied to the input. this has the advantage of very little power being tapped off in rf power transmission applications.
ad8314 C12C rev. a table ii. recommended components for x1 and x2 in figure 32b frequency voltage gain (ghz) x1 x2 (db) 0.1 short 52.3 ? 0.9 33 nh 39 nh 11.8 1.9 10 nh 15 nh 7.8 2.5 1.5 pf 3.9 nh 2.55 increasing the logarithmic slope in measurement mode the nominal logarithmic slope of 21.5 mv/db (see tpc 7 for the variation of slope with frequency) can be increased to an arbitrarily high value by attenuating the signal betw een v_up and vset as shown in figure 9. the ratio r1/r2 is set using the equation: r 1 /r 2 = ? ? ? ? ? ? new slope original slope 1 in the example shown, two 5 k ? resistors combine to change the slope at 1900 mhz from 20 mv/db to 40 mv/db. the slope can be increased to higher levels. this will, however, reduce the usable dynamic range of the device. ad8314 r1 5k v_up vset 40mv/db @ 1900mhz r2 5k figure 9. increasing the output slope effect of waveform type on intercept although speci ed for input levels in dbm (db relative to 1 mw), the ad8314 fundamentally responds to voltage and not to power. a direct consequence of this characteristic is that input signals of equal rms power but differing crest factors will produce different results at the log amp s output. the effect of differing signal waveforms is to shift the effective value of the intercept upwards or downwards. graphi cally, this looks like a vertical shift in the log amp s transfer function. the logarithmic slope, however, is not affected. for example, consider the case of the ad8314 being alternately fed by an unmodulated sine wave and by a single cdma channel of the same rms power. the ad8314 s output voltage will differ by the equivalent of 3.55 db (70 mv) over the complete dynamic range of the device (the output for a cdma input being lower). table iii shows the correction factors that should be applied to measure the rms signal strength of a various signal types. a sine wave input is used as a reference. to measure the rms power of a square wave, for example, the mv equivalent of the db value given in the table (20 mv/db times 3.01 db) should be subtracted from the output voltage of the ad8314. table iii. shift in ad8314 output for signals with differing crest factors correction factor (add to measured signal type input level) sine wave 0 db square wave 3.01 db gsm channel (all time slots on) 0.55 db cdma channel (forward link, 3.55 db 9 channels on) cdma channel (reverse link) 0.5 db pdc channel (all time slots on) 0.58 db mobile handset power control examples figure 10 shows a complete power amplifier control circuit for a dual mode handset. this circuit is applicable to any dual mode handset using tdma or cdma technologies. the pf08107b (hitachi) is driven by a nominal power level of +3 dbm. some of the output power from the pa is coupled off using an ldc15d190a0007a (murata) directional coupler. this has a coupling factor of approximately 19 db for its lower frequency band (897.5 17.5 mhz) and 14 db for its upper band (1747.5 37.5 mhz) and an insertion loss of 0.38 db and 0.45 db respectively. because the pf08107b transmits a maximum p ower level of +35 dbm, additional attenuation of 15 db is r equired before the coupled signal is applied to the ad8314. 1 2 3 4 enbl rfin ad8314 8 7 6 5 vset fltr vpos comm v up +v s 2.7v vset 0v 1.1v pf081807b (hitachi) pin band 1 +3dbm pin band 2 +3dbm 1000pf 0dbm max +v s attn 15db v dn c f 220pf pout band 2 +32dbm max pout band 1 +35dbm max 4.7 f to antenna 49.9 7 8 5 1 4 3 26 ldc15d190a0007a band select 0v/2v 3.5v v ctl v apc 0.1 f 52.3 figure 10. a dual mode power ampli?er control circuit
ad8314 C13C rev. a the setpoint voltage, in the range 0 v to 1.1 v, is applied to the vset pin of the ad8314. this will typically be supplied by a digital-to-analog converter (dac). this voltage is compared to the input level of the ad8314. any imbalance between vset and the rf input level is corrected by v_dn, which drives the v apc (gain control) of the power ampli er. v_dn reaches a maximum value of approximately 1.9 v on a 2.7 v supply (this will be higher for higher supply voltages) while delivering approxi- mately 3 ma to the v apc input. a lter capacitor (c f ) must be used to stabilize the loop. the choice of c f will depend to a large degree on the gain control dynamics of the power ampli er, something that is frequently poorly characterized, so some trial and error may be necessary. in this example, a 220 pf capacitor gives the loop sufficient speed to follow the gsm and dcs1800 time slot ramping profiles, while still having a stable, critically damped response. figure 11 shows the relationship between the setpoint voltage, v set and output power, at 0.9 ghz. the overall gain control function is linear in db for a dynamic range of over 40 db. figure 12 shows a similar circuit for a single band handset power amplifier. the bgy241 (phillips) is driven by a nominal power level of 0 dbm. a 20 db directional coupler, dc09-73 (alpha) is used to couple the signal in this case. figure 13 shows the relation- ship between the control voltage and the output power at 0.9 ghz. in both of these examples, noise on the v_dn pin can be reduced by placing a simple rc low-pass filter between v dn and the gain control pin of the power amplifier. however, the value of the resistor should be kept low to minimize the voltage drop across it due to the dc current flowing into the gain control input. vset v 30 0 pout dbm 0.2 0.4 0.6 0.8 1.0 1.2 20 10 0 10 20 30 40 figure 11. pout vs. vset at 0.9 ghz for dual mode handset power ampli?er application enbl rfin ad8314 vset fltr vpos comm v up v s 2.7v v set 0v 1.1v rf input 0dbm max v s attn 15db v dn c f 220pf +35dbm max 47 f to antenna bgy241 +15dbm 2.2 f 680pf p in 0dbm dc09-73 6 3 4 5 12 3.5v 0.1 f 52.3 figure 12. a single mode power ampli?er control circuit vset v 30 0 pout dbm 0.2 0.4 0.6 0.8 1.0 20 10 0 10 20 30 40 40 50 figure 13. pout vs. vset at 0.9 ghz for single mode handset
ad8314 C14C rev. a 1 2 3 4 enbl rfin ad8314 8 7 6 5 vset fltr vpos comm v up c1 0.1 f v pos r2 52.3 vset v dn c4 (open) r8 (open) r7 0 lk1 input r1 0 sw1 r3 0 r4 (open) c2 (open) v dn v up r5 0 r6 (open) c3 (open) vpos r9 0 figure 16. evaluation board schematic operation at 2.7 ghz while the ad8314 is specified to operate at frequencies up to 2.5 ghz, it will work at higher frequencies, although it does exhibit slightly higher output voltage temperature drift. figure 14 shows the transfer function of a typical device at 2.7 ghz, at ambient as well as hot and cold temperatures. figure 15 shows the transfer function of the ad8314 when driven by both an unmodulated sine wave and a 64 qam signal. as already discussed, the higher peak-to-average ratio of the 64 qam signal causes an increase in the intercept. in this case the intercept increases by about 1.5 db, causing the overall transfer function to drop by the same amount. for precision operation, the ad8314 should be calibrated for each signal type that is driving it. using the chip scale package on the underside of the chip scale package, there is an exposed compressed paddle. this paddle is internally connected to the chip s ground. while the paddle can be connected to the printed circuit board s ground plane, there is no thermal or electrical requirement to do this. evaluation board figure 16 shows the schematic of the ad8314 so evaluation board. the layout and silkscreen of the component side are shown in figures 17 and 18. an evaluation board is also avail- able for the csp package. (for exact part numbers, see ordering guide.) apart from the slightly smaller device footprint, the csp evaluation board is identical to the so board. the board is powered by a single supply in the range, 2.7 v to 5.5 v. the power supply is decoupled by a single 0.1 f capacitor. addi- tional decoupling, in the form of a series resistor or inductor in r9, can also be added. table iv details the various con guration options of the evaluation board. input power dbm 70 v up v 60 50 40 30 20 0.4 0.6 0.8 1.0 1.2 0.2 0.0 10 0 10 cw error db 1 0 1 2 3 2 3 cw 64 qam 64 qam figure 15. shift in transfer function due to 64 qam input power dbm 70 v up v 60 50 40 30 20 0.4 0.6 0.8 1.0 1.2 0.2 0.0 10 0 10 +25 c 30 c +25 c 30 c +80 c +80 c error db 1 0 1 2 3 2 3 figure 14. operating at 2.7 ghz
ad8314 C15C rev. a table iv. evaluation board con?uration options component function default condition tp1, tp2 supply and ground vector pins not applicable sw1 device enable: when in position a, the enbl sw1 = a pin is connected to +v s and the ad8314 is in operating mode. in position b, the enbl pin is grounded, putting the device in power-down mode. r1, r2 input interface: the 52.3 ? resistor in position r2 = 52.3 ? (size 0603) r2 combines with the ad8314 s internal input r1 = 0 ? (size 0402) impedance to give a broadband input impedance of around 50 ? . a reactive match can be imple- mented by replacing r2 with an inductor and r1 (0 ? ) with a capacitor. note that the ad8314 s rf input is internally ac-coupled. r3, r4, c2, r5, r6, c3 output interface: r4, c2, r6, and c3 can be r4 = c2 = r6 = c3 = open (size 0603) used to check the response of v_up and v_dn r3 = r5 = 0 ? (size 0603) to capacitive and resistive loading. r3/r4 and r5/r6 can be used to reduce the slope of v_up and v_dn. c1, r9 power supply decoupling: the nominal supply c1 = 0.1 f (size 0603) decoupling consists of a 0.1 f capacitor (c1). a r9 = 0 ? (size 0603) series inductor or small resistor can be placed in r9 for additional decoupling. c4 filter capacitor: the response time of v_up c4 = open (size 0603) and v_dn can be modi ed by placing a capacitor between fltr (pin 4) and v_up. r7, r8 slope adjust: by installing resistors in r7 and r8, r7 = 0 ? (size 0603) the nominal slope of 20 mv/db can be increased. r8 = open (size 0603) see slope adjust discussion for more details. lk1 measurement/controller mode: lk1 shorts lk1 = installed v_up to vset, placing the ad8314 in measurement mode. removing lk1 places the ad8314 in controller mode. figure 17. layout of component side ( so) figure 18. silkscreen of component side ( so)
C16C c01086C0C 3/02(a) printed in u.s.a. rev. a outline dimensions dimensions shown in inches and (mm). 8-lead micro_soic (rm-8) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) 8-lead chip scale (cp-8) 1.89 1.74 1.59 0.50 bsc 0.30 0.23 0.18 0.60 0.45 0.30 0.55 0.40 0.30 seating plane 12 0 0.25 ref 0.05 0.02 0.00 1.00 0.90 0.80 3.25 3.00 2.75 1.95 1.75 1.55 2.95 2.75 2.55 pin 1 indicator 2.25 2.00 1.75 notes 1. controlling dimensions are in millimeters. 2. paddle is copper plated with lead finish. 0.15 0.10 0.05 0.25 0.20 0.15 bottom view 4 58 1 ad8314 revision history location page data sheet changed from rev. 0 to rev. a. edit to product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to tpc 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 new section (operation at 2.7 ghz) added. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 addition of new figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 changes to evaluation board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 addition of chip scale package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

▲Up To Search▲

Price & Availability of AD8314ARMZ-REEL7

	To Download AD8314ARMZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .